The present invention relates to integrated comparator circuits and, more particularly, to such comparators comprising a pair of input transistors adapted to receive a differential input signal for driving a current source transistor of same conductivity type which has its base coupled to an output of the comparator. More particularly, the subject invention is concerned with eliminating or severely reducing any offset voltage that is introduced by the loading effect of the current source transistor.
PNP comparator circuits which are operated from a single power supply are well known in the art. A problem occurs if a PNP comparator must be operated from a single power supply to provide an output signal to drive a current sourcing PNP transistor at the output of the comparator. For example, one such use for a PNP comparator is in an overvoltage sensing circuit wherein one input to the comparator is connected to a fixed reference potential while the other input is coupled to a voltage to be sensed. It may be desirable to switch the conduction state of the comparator at a particular value of the sensed voltage. The aforementioned problem arises due to the base current flowing from the PNP current source transistor into the output of comparator. Since the forward current gain factor, beta, of the PNP transistors is typically small for PNP transistors fabricated in monolithic form, the base current produces a loading effect on the comparator which reflects onto the input thereof as an offset voltage. This offset voltage offsets the balanced switching point of the comparator which may be undesirable.
Thus, there is a need for canceling the effects of the base current error into the output of the comparator described above.